AMCC PPC405 User Manual

PPC405CR – AMCC® PowerPC® 32-bit RISC Processor Summary Core Reference CR0161 (v2.0) March 11, 2008 This document provides information on Altium De

PPC405CR – AMCC PowerPC 32-bit RISC Processor Memory & I/O Management The PPC405CR uses 32-bit address buses providing a 4GByte linear address spa

PPC405CR – AMCC PowerPC 32-bit RISC Processor Figure 5. Memory devices mapped into the PPC405CR's address space. Figure 6. Peripheral devices

PPC405CR – AMCC PowerPC 32-bit RISC Processor The adjacent flow chart shows the process that was followed to build this memory map in the FPGA project

PPC405CR – AMCC PowerPC 32-bit RISC Processor This memory still has the standard limitation of load delay slots, because the load from memory happen

PPC405CR – AMCC PowerPC 32-bit RISC Processor 0xFFFF_FFE4 mtdcr PeripheralControl_Data,%R4; Memory controller now configured. Now jump out to a

PPC405CR – AMCC PowerPC 32-bit RISC Processor Word-0 Word-1 31 24 23 16 15 8 7 0 31

PPC405CR – AMCC PowerPC 32-bit RISC Processor 8-bit peripheral devices should be accessed using the 8-bit LBU and SB instructions. For C-code, this me

PPC405CR – AMCC PowerPC 32-bit RISC Processor Wishbone Communications The following sections detail the standard handshaking that takes place when t

PPC405CR – AMCC PowerPC 32-bit RISC Processor Reading from a Slave Wishbone Memory Device Data is read by the host processor (Wishbone Master) from a

PPC405CR – AMCC PowerPC 32-bit RISC Processor Placing a PPC405CR in an FPGA Design Figure 9 shows an example of how a PPC405CR is used within an FPG

PPC405CR – AMCC PowerPC 32-bit RISC Processor RISC Processor Background RISC, or Reduced Instruction Set Computer, is a term that is conventionally us

PPC405CR – AMCC PowerPC 32-bit RISC Processor Figure 10. Detected physical devices appearing in the Hard Devices JTAG chain. As the physical PPC405CR

PPC405CR – AMCC PowerPC 32-bit RISC Processor Downloading Your Design Download of a design which incorporates a discrete processor such as the PPC40

PPC405CR – AMCC PowerPC 32-bit RISC Processor On-Chip Debugging To facilitate real-time debugging of the processor, the PPC405CR includes On-Chip Debu

PPC405CR – AMCC PowerPC 32-bit RISC Processor The debug environment offers the full suite of tools you would expect to see in order to efficiently d

PPC405CR – AMCC PowerPC 32-bit RISC Processor Full-feature debugging is of course enjoyed at the source code level – from within the source code file

PPC405CR – AMCC PowerPC 32-bit RISC Processor For more information on the content and use of processor debug panels, press F1 when the cursor is ove

PPC405CR – AMCC PowerPC 32-bit RISC Processor Improving and Extending Product Life-Cycles Fast time to market is usually synonymous with a weaker fe

PPC405CR – AMCC PowerPC 32-bit RISC Processor Wishbone OpenBUS Processor Wrappers To normalize access to hardware and peripherals, each of the 32-bit

PPC405CR – AMCC PowerPC 32-bit RISC Processor Architectural Overview Symbol Figure 1. PPC405CR symbol. As can be seen from Figure 1 (previous), the

PPC405CR – AMCC PowerPC 32-bit RISC Processor Pin Description Table 1. PPC405CR pin description Name Type Polarity/Bus size Description Control Signal

PPC405CR – AMCC PowerPC 32-bit RISC Processor Name Type Polarity/Bus size Description IO_ACK_I I High Standard Wishbone device acknowledgement signa

PPC405CR – AMCC PowerPC 32-bit RISC Processor Name Type Polarity/Bus size Description PER_READY O High External Wait Control. Allows external devices

PPC405CR – AMCC PowerPC 32-bit RISC Processor • 1KB (256 x 32-bit Words) • 2KB (512 x 32-bit Words) • 4KB (1K x 32-bit Words) • 8KB (2K x 32-bit Wo